The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having a compact cell size and a method for the manufacture thereof.
As is well known, a dynamic random access memory (DRAM) having a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged a capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
In attempt to meet the demand, there have been proposed a ferroelectric memory (FeRAM) where a capacitor thin film with ferroelectric properties such as strontium bithmuth tantalate (BST) is used for capacitors in place of conventional silicon oxide film or silicon nitride film.
In FIG. 1, there is shown a cross sectional view setting forth a conventional semiconductor memory device 100 for use as FeRAM. The semiconductor memory device 100 includes an active matrix 10 incorporating a metal oxide semiconductor (MOS) transistor therein, a capacitor structure 24 having a bottom electrode, a capacitor thin film and a top electrode, a bit line 34 and a metal interconnection 36.
In FIGS. 2A to 2E, there are illustrated manufacturing steps involved in manufacturing a conventional semiconductor memory device 100 shown in FIG. 1.
The process for manufacturing the conventional semiconductor memory device 100 begins with the preparation of an active matrix 10 having a silicon substrate 2, a MOS transistor formed thereon as a selective transistor, an isolation region 4 and a first insulating layer 16 formed on the MOS transistor and the isolation region 4. The MOS transistor includes diffusion regions 6 as a source and a drain, a gate oxide 8, a spacer 14 and a gate electrode 12.
In a subsequent step, there is formed on top of the active matrix 10 a first metal layer 18, a dielectric layer 20 and a second metal layer 22, sequentially, as shown in FIG. 2A. Both of the metal layers 18, 22 are formed of titanium (Ti) and platinum (Pt) in which Ti is used for an adhesive layer. The dielectric layer 20 is made of a ferroelectric material. The first and the second metal layers 18, 22 are deposited with a sputter and the dielectric layer 20 is spin-on coated.
Thereafter, the second metal layer 22 and the dielectric layer 20 are patterned into a predetermined configuration. And then, the first metal layer 18 is patterned into a second predetermined configuration by using a photolithography method, thereby obtaining a capacitor structure 24 having a bottom electrode 18A, a capacitor thin film 20A and a top electrode 22A, as shown in FIG. 2B.
In a next step, a second insulating layer 26, e.g., made of silicon dioxide (SiO2), is formed on top of the active matrix 10 and the capacitor structure 24 by using a plasma chemical vapor deposition (CVD), as shown in FIG. 2C.
In an ensuing step, openings 28, 30, 32 are formed in the second insulating layer 26 and the first insulating layer 16 of the active matrix 10 at positions over the diffusion regions 6 of the MOS transistor and the capacitor structure 24 by reactive ion etching (RIE), as shown in FIG. 2D.
Finally, a metal interconnection layer is formed over the entire surface including the interiors of the openings 28, 30, 32, and is patterned to form a bit line 34 and a metal interconnection 36, as shown in FIG. 2E.
One of the major shortcomings of the above-described semiconductor memory device 100 and the method for the manufacture thereof is that it is difficult to decrease the cell area thereof since the location of the capacitor structure 24 is not aligned with that of the MOS transistor in vertical direction.
It is, therefore, an object of the present invention to provide a semiconductor memory device having a reduced cell area by forming a capacitor structure at a position over a transistor.
It is another object of the present invention to provide a method for manufacturing a semiconductor memory device having a reduced sized by forming a capacitor structure at a position over a transistor.
In accordance with one aspect of the present invention, there is provided a semiconductor memory device, including: an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate and a field oxide for isolating the transistor; a first metal line formed on top of the active matrix and extending outside the transistor; a capacitor structure formed over the transistor; and a second metal line formed on top of the capacitor structure to electrically connect the capacitor structure to the transistor through the first and the second metal line.
In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the method comprising the steps of: a) preparing an active matrix provided with a semiconductor substrate and a transistor formed on top of the semiconductor substrate; b) forming a first metal layer and pattering the first metal layer into a first predetermined configuration to obtain a first metal line for electrically connecting the transistor thereto; c) forming an insulating layer on top of the first metal line; d) forming a capacitor structure at a position over the transistor; and e) forming a second metal layer and patterning into a second predetermined configuration to electrically connect the second metal line to the first metal line.